1. Field of the Invention
The present invention provides a method for determining output signals of a Viterbi decoder, and more particularly, a method for determining the output signals according to difference between the sum of digital signals provided by a path memory module and the half of state number.
2. Description of the Prior Art
Maximum likelihood sequence estimation, or MLSE, has been utilized in a plurality of digital decoders generally, where a Viterbi detector is one of those circuits detecting convolution codes based on MLSE. As those skilled in the art recognize, a communication channel always includes additive white Gaussian noise, (or AWGN), or other forms of interference, so that a communication system encodes data prior to transmission for decreasing detection errors after the data is received. For example, by application of a specific algorithm, a given amount of data is convoluted to include more data bits prior to transmission. Based on the algorithm, the communication system can detect whether the received data is correct or not, and even correct erroneous bits in the data.
Please refer to FIG. 1, which illustrates a block diagram of a prior art Viterbi decoder 10. The Viterbi decoder 10 includes a branch metric unit 12, an add-compare-select unit 14, a path memory module 18, a path metric memory module 16 and an output selector 20. The branch metric unit 12 receives a sequence of signals DTi, and transmits the signals DTi to the add-compare-select unit 14 through a plurality of branch paths according to a default setting of the Viterbi decoder 10. The add-compare-select unit 14 determines path metrics of the signals DTi by means of a Viterbi algorithm based on MLSE, and outputs the path metrics to the path metric memory module 16. Meanwhile, the add-compare-select unit 14 calculates a plurality of state values and outputs to the path memory module 18. The output selector 20 determines a sequence of output signals DTo according to signals outputted from the path memory module 18. Operations of the Viterbi decoder 10 are well known in the art, so no further details of such are disclosed herein. As to the output selector 20 of the Viterbi decoder 10, take partial response PR (1,2,2,2,1) for example. Please refer to FIG. 2, which illustrates a configuration diagram of the output selector 30 with state number 10. The output selector 30 includes a minimum selector 32 and an output module 33. The minimum selector 32 includes ten input terminals I0˜I9 and ten output terminals O0˜O9 for receiving digital signals provided by the path memory module 18 through the input terminals I0˜I9, and outputting the signals from the output terminals O0˜O9 to the output module 33, while the output module 33 includes ten AND gates 34 and three OR gates 36. Please refer to FIG. 3, which illustrates a table of output signals of the minimum selector 32. In FIG. 3, the second column of the table represents different situations of the minimum selector 32, and the first column represents output signals corresponding to the situations in the second column.
Therefore, with the output selector 30, the prior art ten-state-number Viterbi decoder can output reliable results. However, as shown in FIG. 2 and FIG. 3, the output selector 30 includes complicated circuits, which costs a lot in terms of system resources. Moreover, with more and more input signals, the output selector becomes more and more complicated, so production costs increase along with the abovementioned drawbacks.